1. Field of the Invention
This invention relates to the improvement of a Bi-CMOS output buffer circuit which is particularly required to have a large current driving ability and high operation speed.
2. Description of the Related Art
Conventionally, a circuit shown in FIG. 1, for example, is known as a Bi-CMOS output buffer circuit which is required to have a large current driving ability and high operation speed.
The operation of the above circuit is described below. First, assume that an input signal is applied to an input terminal 901. In this case, a P-channel MOSFET 902 is set in the OFF state and an N-channel MOSFET 903 is set in the ON state. Therefore, the base potential of an NPN bipolar transistor 904 is substantially set to an "L (GND)" level, thereby turning off the transistor 904. The voltage V.sub.IN of "H" level applied to the input terminal 901 is applied to an inverter 905. That is, a non-inverted signal (in this case, a voltage of "H" level) of the input signal V.sub.IN is applied to the base of a transistor 907. As a result, the transistor 907 is turned on, thus causing an output voltage V.sub.OUT of "H" level to be output from an output terminal 908.
Next, assume that a voltage V.sub.IN of "L (low)" level is applied to the input terminal 901. In this case, a voltage of "L" level is applied to the base of the transistor 907 to turn off the transistor 907. At this time, the P-channel MOSFET 902 is set in the ON state and the N-channel MOSFET 903 is set in the OFF state. Therefore, the base potential of the transistor 904 rises to turn on the transistor 904, thereby causing an output potential V.sub.OUT of "L" level to be output from the output terminal 908.
In the above output buffer circuit, an N-channel MOSFET 909 of the inverter 906 is turned on when the input signal V.sub.IN is changed from the "H" level (for example, 5 V) to the "L" level (for example, 0 V). As a result, the base potential of the transistor 907 is set to substantially 0 V and the transistor 907 is turned off. At this time, since the P-channel MOSFET 902 is set into the ON state, the base potential of the transistor 904 rises and a current flows into the base thereof. Therefore, the transistor 904 is turned on so that the output potential V.sub.OUT of the output terminal 908 may be changed from the "H" level to the "L" level.
However, as shown in FIG. 2, a phenomenon called "undershoot" is caused by the flow of a transition current i and the presence of parasitic inductance L.sub.P of a bonding wire or the like in the above output buffer circuit. The phenomenon is a well-known phenomenon that the output potential V.sub.OUT is temporarily set to be negative (below the GND level) and can be expressed by an equation of L.sub.P .times.di/dt.
The undershoot causes the value of the output potential V.sub.OUT to be lower than -V.sub.F. As a result, the base potential of the transistor 907 is set to a value obtained by adding the peak value (-V.sub.USP) of the undershoot to the threshold voltage V.sub.F of the transistor 907, that is, a value equal to or lower than 0 V.
Therefore, as shown in FIG. 1, a potential difference occurs between the source and drain of the N-channel MOSFET 909 of the inverter 906 and a current i.sub.l flows into the base of the transistor 907 from V.sub.SS (GND level). As a result, the transistor 907 which must be kept in the OFF state will be set into the ON state, thereby causing a large collector current to flow in the transistor 907.
Therefore, as shown in FIG. 3, the power source voltage V.sub.DD becomes unstable or fluctuates because of the flow of a collector current and the presence of the inductance (L.sub.P) component of the power source V.sub.DD line. In this case, a plurality of logic circuits such as the above output buffer circuit are contained in the LSI, and in general, the logic circuits are commonly connected to the power source V.sub.DD. Therefore, the output voltage V'.sub.OUT of a logic circuit 911 which is arranged near the above output buffer circuit 910 may fluctuate. The degree of fluctuation in the output voltage V'.sub.OUT may exceed the circuit threshold voltage of the next-stage logic circuit connected to the logic circuit 911, and in this case, the next-stage logic circuit may be erroneously operated.